"The prevailing VLSI design scenario is outlined by increasing design sizes, complex functionality
and decreased time-to-market. This leads to high levels of integration on a single chip, called
the System on Chip (SoC). As integration levels on a SoC advance at a rapid pace and design
reuse becoming indispensable to meet current VLSI challenges, need for efficient on-chip interconnects
to connect various semiconductor Intellectual Property (IP) blocks on SoC also rises. Approaches
adopted to aid plug and play style IP reuse include the development of the standard
on-chip bus communication architectures. Nowadays, Advanced Microcontroller Bus Architecture
(AMBA) is one of the leading on-chip bus protocol for the blocks to interface with each other
in high-performance SoC design.
Also with ever increasing design complexity, and use of bus standards to intensify reusability
of IP cores, one of the biggest challenges in chip design is to ensure that design works accurately.
In order to establish reliable functioning of these designs, Functional Verification (FV) is required
to be carried out comprehensively.
In presented work, verification step in digital design cycle is thoroughly studied with Stateof-
the-art Verification Languages like System Verilog and methodologies like Open Verification
Methodology (OVM) and Universal Verification Methodology (UVM). Also, AMBA’s Advanced
Peripheral Bus(APB) protocol for SoC integration is studied, and FV of APB is carried out exhaustively
in System Verilog (SV) employing specialized constructs and techniques like constraint random
stimulus generation, transaction modeling, assertions and various coverage metrics.
i"