Assertion Based Coverage Driven Functional Verification of Advanced Peripheral Bus Protocol (Record no. 14684)

MARC details
000 -LEADER
fixed length control field 02284nam a22001697a 4500
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.3
Item number R257A
100 ## - MAIN ENTRY--AUTHOR NAME
Personal name Rawal, Saurabh
245 ## - TITLE STATEMENT
Title Assertion Based Coverage Driven Functional Verification of Advanced Peripheral Bus Protocol
Statement of responsibility, etc by Saurabh Rawal
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Place of publication IIT Jodhpur
Name of publisher Department of Electrical Engineering
Year of publication 2017
300 ## - PHYSICAL DESCRIPTION
Number of Pages x,43p.
Other physical details HB
520 ## - SUMMARY, ETC.
Summary, etc "The prevailing VLSI design scenario is outlined by increasing design sizes, complex functionality<br/>and decreased time-to-market. This leads to high levels of integration on a single chip, called<br/>the System on Chip (SoC). As integration levels on a SoC advance at a rapid pace and design<br/>reuse becoming indispensable to meet current VLSI challenges, need for efficient on-chip interconnects<br/>to connect various semiconductor Intellectual Property (IP) blocks on SoC also rises. Approaches<br/>adopted to aid plug and play style IP reuse include the development of the standard<br/>on-chip bus communication architectures. Nowadays, Advanced Microcontroller Bus Architecture<br/>(AMBA) is one of the leading on-chip bus protocol for the blocks to interface with each other<br/>in high-performance SoC design.<br/>Also with ever increasing design complexity, and use of bus standards to intensify reusability<br/>of IP cores, one of the biggest challenges in chip design is to ensure that design works accurately.<br/>In order to establish reliable functioning of these designs, Functional Verification (FV) is required<br/>to be carried out comprehensively.<br/>In presented work, verification step in digital design cycle is thoroughly studied with Stateof-<br/>the-art Verification Languages like System Verilog and methodologies like Open Verification<br/>Methodology (OVM) and Universal Verification Methodology (UVM). Also, AMBA’s Advanced<br/>Peripheral Bus(APB) protocol for SoC integration is studied, and FV of APB is carried out exhaustively<br/>in System Verilog (SV) employing specialized constructs and techniques like constraint random<br/>stimulus generation, transaction modeling, assertions and various coverage metrics.<br/>i"<br/>
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical Term Advanced Peripheral Bus Protocol
Topical Term MTech Theses
Topical Term Department of Electrical Engineering
700 ## - ADDED ENTRY--PERSONAL NAME
Personal name Tiwari, Shree Prakash
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type Thesis
Holdings
Withdrawn status Lost status Damaged status Not for loan Collection code Permanent Location Current Location Shelving location Date acquired Full call number Accession Number Price effective from Koha item type
      Not For Loan Reference S. R. Ranganathan Learning Hub S. R. Ranganathan Learning Hub Course Reserve 2024-01-18 621.3 R257A TM00107 2024-01-18 Thesis