"Phase Locked Loop (PLL) is one of the most important component in design of electronic products.
It has wide variety of applications that includes clock recovery and generation, frequency
synthesis, data recovery etc. PLL is a mixed signal circuit that consist of both analog and digital signal
processing units. Due to advancement in technology as well as applications, the requirements
like high operating frequency, shorter lock time, high sensitivity, more robustness, low jitter and
phase noise are in demand. For low operating frequency PLLs, these parameters are little difficult
to achieve. One method to achieve these is by Symmetrical designing of PLL circuit components.
The advantage of symmetricity is that they usually enhance the performance and minimize the
process and temperature variations.
A Phase Frequency Detector (PFD) and Frequency divider (FD) are two important digital circuits
that work with clock inputs and outputs of a PLL. The conventional PFD compares the two incoming
frequencies in phase or frequency and for that, it has to be a precise one and highly sensitive.
Over the years, many adaptations in the design of PFD has been made in order to improve the error
detection range which needs to be wider for a better PLL. In 180 nm technology, for low operating
frequency range, a conventional D flip-flop based PFD generally has unsymmetrical design and
low phase/frequency error detection range because of drawbacks like Deadzone and Blindzone.
Because of this, PLL may get locked to incorrect frequencies. The present work focusses on designing
this conventional D flip-flop based PFD, first with a symmetric design and second, with a
view of eliminating this Deadzone and Blindzone completely. On other hand, Frequency Divider
is designed for a wide frequency range with basic D flip flops by designing a divide by 4 circuit.
The Proposed PFD has zero deadzone which increases its phase sensitivity and a blindzone comprising
of approximately 25% of the total error detection range. This is because of the trade off
between the two. Along with it, symmetricity is achieved at each hierarchical level with approximately
equal rise and fall time of output. In final stage, a PLL is integrated with symmetric circuit
blocks of PFD, Charge Pump and Loop Filter (CP+LF), Voltage Controlled Oscillator (VCO) and
FD. The designed PLL has an input frequency range of 11 to 58 MHz and output frequency range
of 44 to 232 MHz with a maximum power dissipation of 1.08 mW.
The circuits are implemented using the Process design Kit (PDK) by Semi-Conductor Laboratory
(SCL) and the designs are based on 180 nm technology with a supply voltage of 1.8 V."