Design of Phase Frequency Detector and Frequency Divider for a Phase Locked Loop in 180 nm Technology (Record no. 14682)

MARC details
000 -LEADER
fixed length control field 03331nam a22001817a 4500
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.3
Item number A796D
100 ## - MAIN ENTRY--AUTHOR NAME
Personal name Arya, Prakriti
245 ## - TITLE STATEMENT
Title Design of Phase Frequency Detector and Frequency Divider for a Phase Locked Loop in 180 nm Technology
Statement of responsibility, etc by Prakriti Arya
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Place of publication IIT Jodhpur
Name of publisher Department of Electrical Engineering
Year of publication 2017
300 ## - PHYSICAL DESCRIPTION
Number of Pages xi,41p.
Other physical details HB
520 ## - SUMMARY, ETC.
Summary, etc "Phase Locked Loop (PLL) is one of the most important component in design of electronic products.<br/>It has wide variety of applications that includes clock recovery and generation, frequency<br/>synthesis, data recovery etc. PLL is a mixed signal circuit that consist of both analog and digital signal<br/>processing units. Due to advancement in technology as well as applications, the requirements<br/>like high operating frequency, shorter lock time, high sensitivity, more robustness, low jitter and<br/>phase noise are in demand. For low operating frequency PLLs, these parameters are little difficult<br/>to achieve. One method to achieve these is by Symmetrical designing of PLL circuit components.<br/>The advantage of symmetricity is that they usually enhance the performance and minimize the<br/>process and temperature variations.<br/>A Phase Frequency Detector (PFD) and Frequency divider (FD) are two important digital circuits<br/>that work with clock inputs and outputs of a PLL. The conventional PFD compares the two incoming<br/>frequencies in phase or frequency and for that, it has to be a precise one and highly sensitive.<br/>Over the years, many adaptations in the design of PFD has been made in order to improve the error<br/>detection range which needs to be wider for a better PLL. In 180 nm technology, for low operating<br/>frequency range, a conventional D flip-flop based PFD generally has unsymmetrical design and<br/>low phase/frequency error detection range because of drawbacks like Deadzone and Blindzone.<br/>Because of this, PLL may get locked to incorrect frequencies. The present work focusses on designing<br/>this conventional D flip-flop based PFD, first with a symmetric design and second, with a<br/>view of eliminating this Deadzone and Blindzone completely. On other hand, Frequency Divider<br/>is designed for a wide frequency range with basic D flip flops by designing a divide by 4 circuit.<br/>The Proposed PFD has zero deadzone which increases its phase sensitivity and a blindzone comprising<br/>of approximately 25% of the total error detection range. This is because of the trade off<br/>between the two. Along with it, symmetricity is achieved at each hierarchical level with approximately<br/>equal rise and fall time of output. In final stage, a PLL is integrated with symmetric circuit<br/>blocks of PFD, Charge Pump and Loop Filter (CP+LF), Voltage Controlled Oscillator (VCO) and<br/>FD. The designed PLL has an input frequency range of 11 to 58 MHz and output frequency range<br/>of 44 to 232 MHz with a maximum power dissipation of 1.08 mW.<br/>The circuits are implemented using the Process design Kit (PDK) by Semi-Conductor Laboratory<br/>(SCL) and the designs are based on 180 nm technology with a supply voltage of 1.8 V."<br/>
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical Term Phase Frequency Detector
Topical Term Frequency Divider
Topical Term MTech Theses
Topical Term Department of Electrical Engineering
700 ## - ADDED ENTRY--PERSONAL NAME
Personal name Tiwari, Shree Prakash
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type Thesis
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      Not For Loan Reference S. R. Ranganathan Learning Hub S. R. Ranganathan Learning Hub Course Reserve 2024-01-18 621.3 A796D TM00105 2024-01-18 Thesis