000			03723nam a22001697a 4500
082			_a621.38 _bC496L
100			_aChauhan, Itisha _926050
245			_aLow Power SRAM Design and Analysis (8*2048 Memory Block in 180 nm & 45 nm Technology Nodes _cby Itisha Chauhan
260			_aIIT Jodhpur _bElectrical Engineering _c2017
300			_ax,43p. _bHB
520			_aSRAM is an important part of integrated systems today. It occupies most of the space in the chip and provides the bottleneck for speed and power analysis for the chip design. Six Transistor Static Random Access Memory (6T SRAM) is a type of semiconductor memory that uses bistable latching circuit to store one bit. This cell is the important component for SRAM memory blocks designed in today’s industrial or academic world. CMOS 6T SRAM cell consumes very less power and is faster than its other alternatives like flip-flops. Signal to Noise Margin (SNM) is an important parameter for a latched memory like SRAM cell which describes the stability of the SRAM. The SRAM has some key considerations like speed, reduced area and low power. In the presented work, a 8x2048 SRAM block was developed and analyzed for low power. As there is a trade off between the three quantities, design considerations for an SRAM memory block becomes crucial and important. The main objective of this project is to compare different technologies (180 nm, 45 nm and 14 nm),analyze the SRAM cell for power optimization and to develop a fully functional memory block of 8x2048 in 45 nm technology and 180 nm technology nodes.Huge designs can take up a lot of human effort and time.To overcome this limitation and increase accuracy in design and analysis, automation is done. One such technique used in industry is schematic design automation using SKILL which is tool command language for cadence virtuoso and stands for silicon compiler interface language. Huge designs can take up a lot of human effort and time. To overcome this limitation and increase accuracy in design and analysis, automation is done. Example of one such automation is migration of complete schematic design from one technology node to another which can be done using a procedure presented as a part of this project in Appendix B. As the size of memory grows, aging and reliability issues come into picture and if circuit consumes more power the aging effect becomes prominent and reliability goes down. As the size of the transistor reduces, the heating effects degrade the transistors’ operations which in turn impacts the reliability of the circuits especially if they are dense enough like an SRAM memory block. This report presents the basic analysis flow called as reliability flow for parameters like Hot Carrie Injection (HCI), Biased Temperature Instability (BTI). Industry deals with each of these effects very carefully using dedicated tools like cadence’s Relexpert for aging and electrical overstress (EOS) analysis. Every design goes through a rigorous reliability check for pre-layout and post-layout designs before it can be fabricated and sent out to customers. Vdd plays a major role in the functionality of a memory block. Results of the proposed memory block in 45 nm technology show that, decreasing operating voltages reduces the power consumption to a significant level however it degrades the timing performance. Also, power dissipation goes down with advancement in technology node which is concluded by comparing power dissipation results in 45 nm and 180 nm technology nodes for 8x2048 memory block.
650			_aLow Power SRAM _926051
650			_aMTech Theses _926052
650			_aElectrical Engineering _926053
700			_aTiwari, Shree Prakash _926054
942			_cTH
999			_c14679 _d14679