"Phase Locked Loop (PLL) is a widely used block in any electronic systems. It has many applications like frequency multiplication, clock recovery, phase/frequency demodulation, and clock
duty cycle correction. They are especially required to generate very stable and accurate clock at high frequency ranges where quartz crystal fails because of its low frequency operation. Growing
demand for high speed systems in modern times has led to increased challenges in the design of PLL.This work focuses on two important blocks of PLL, namely, Voltage Controlled Oscillator (VCO)
and Charge Pump and Loop Filter (CPLF). VCO converts the input control voltage into appropriate frequency. A typical VCO has many design requirements like tuning range, tuning linearity, phase
noise, etc. Linearity is an important design parameter of VCO and efforts are made to improve it. It is designed using a ring oscillator which has advantages like less area and wide tuning range. A
Charge Pump converts the digital outputs from Phase Frequency Detector (PFD) into appropriate control voltage. It should be insensitive to power supply variations and must give a constant value
of current, which is fed into the Loop Filter. Differential ended design can provide such requirements and is preferred over single ended charge pump design. Resistor and Capacitors used in
Loop Filter are required for stability and integration of current respectively.Current Starved VCO (CSVCO) and CPLF are designed using Semi-Conductor Laboratory (SCL)
– Process Design Kit (PDK) Library for a stable PLL. Focus of this work is to achieve a symmetric design, where rise and fall time are equal for low operating frequencies. The design of VCO consists
of 15 stages that gives frequency range of 30 MHz to 200 MHz for input voltage range of 0.5 V to 1.05 V and is further optimized to improve the linearity of frequency variation with input voltage
using resistor to gain more control over VCO frequency range. CPLF is designed using differential ended switches. Loop filter values are calculated in such a way that PLL is stable. Designed PLL is
of type 2 and order 3.The design of proposed schematics and layout is implemented using Cadence Virtuoso Schematic Editor. Schematics are simulated using Synopsys HSpice in 180 nm technology
for the supply voltage of 1.8 V. Layout v/s schematic check is carried by Mentor Graphics Calibre Tool.PLL is found to be stable in the output frequency range of 44 MHz to 232 MHz. Maximum power dissipation of PLL is found to be 1.08mW.
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