TY  - BOOK
AU  - Verma, Shivam
AU  - Tiwari, Shree Prakash
TI  - Design of Low Power SRAM Based Memory: Study and Characteriztion of 1024X8 bit SRAM Memory in 180nm Technology
U1  - 621.395 62 
PY  - 2018///
CY  - IIT Jodhpur
PB  - Department of Electrical Engineering
KW  - SRAM Based Memory
KW  - MTech Theses
KW  - Department of Electrical Engineering
N2  - Memory  arrays  are  an  important  part  of  any  digital  integrated  system.  Over  the  years,  due  to the  dawn  of  low  power  and  high  integrated  density  electronic  gadgets  such  as  Mobile,  Computers  etc.  there  was  a  great  necessity  of  technology  progression  in  memory  chip  design.  Static  random  access  memory  (SRAM)  has  also  gone  through  these  technology  advancement  phases. Many topologies of SRAM cell and other peripherals which are used in memory blockhave been proposed over the years to reduce the power consumption as well as area of system on chip (SoC).  In memories, there is always a tradeoff between power consumption and speedof  operation.  Hence,  it  is  always a  challenging  task  in  memory  designing to  keep  both  these  parameters i.e. Power consumption and speed balanced, while keeping minimum area of SoC. A conventional 6T SRAM cell dominates among various other topologies such as 8T, 5T, 4T and Loadless  4T  SRAM  cell  because  of  its  advantages  such  as  higher  cell  stability  at  lower  supply  voltages  and  lower  process  complexity  etc.  6T  SRAM  cell  uses  two  cross  coupled  CMOS  inverters forming a bi-stable latch for data retention. SRAM is a volatile memory which means data stored in it retained till the power is ON. SRAM is generally used in microprocessors as a cache memory because of its high processing speed.      In this thesis, a 1KB (1024X8bit) SRAM memory is designed which utilizes 6T SRAM cell as core  storing  component.  This  memory  block is  designed  in  cadence  virtuoso  platform  with  HspiceD  simulator  using  SCL_PDK  library  in  180  nm  CMOS  technology  which  utilizes  1.8  V  supply  voltage.  This  SRAM  memory  comprises  of  various  peripherals  circuit  for  proper  read  and  write  operation  which  are  mainly  precharge  circuit,  row  decoder,  column  decoder/mux,  word  line  driver,  sense  amplifier  and  write  driver  circuit  therefore these  peripherals  are  also  designed  and  analyzed.  The  layout  of  6T SRAM  cell  along  with  other  peripherals  is  drawn considering   the   minimum   area   consumption   and   the   Post   layout   simulation   has   been   performed.  Designed  SRAM memory  was also  characterized  for  cell  stability,  access  time  and  power consumption during read and write operation. The cell stability in SRAM is quantified as noise  margin.  Stability  analysis  of  6T  SRAM  cell  is  done  by  studying  butterfly  diagram/eye  diagram  during  hold,  read  and  write  operation.  Static  noise  margin  (hold  mode),  read  noise  margin (read mode) and write noise margin (write mode) are found to be 550 mV, 350 mV and 580 mV respectively which matched with high performance 6T SRAM cell demonstrated in 180 nm  technology.  In  memories,  access  time  signifies  the  performance  of  the  system,  for  1KB  SRAM memory during Read and write operation it is found to be 5 ns and 3.5 ns respectively. The  average  power  consumption  for  1  bit  SRAM  and  1KB  SRAM  memory  for  read  and  write  operation was found to be 43.9 μW and 4.86 mW respectively which are moderate

ER  -