For integrated circuits to be used in space and aeronautical applications, there are challenges which conventional integrated/logic circuits cannot often handle. Due to radiation in space and upper layer of the atmosphere, there are radiation hits on the circuit which can cause a soft error in the circuit at the node where the radiation particle strikes, eventually leading to the state/logic of the circuit to change [1]. Hence, designs are required to address such soft error issues. These designs are called radiation hardened or single event upset (SEU) tolerant. To create a SEU tolerant design, use of redundancy in circuits is often exploited. The idea behind the use of redundancy in the circuit is that in the event of a SET, when one state is affected, the other states that are unaffected can be used to get the correct state of the circuit. With an appropriate decision circuit the output can be taken from the remaining states, thus making the design SEU tolerant [2]. Designs for redundant state logic have also evolved accordingly, however, many formerly used designs had more number of transistors/area [3]. There is always an area- power-critical charge trade off in circuits while designing SEU tolerant circuits.In this work, an SEU tolerant D flip-flop is designed in SCL PDK with 180nm CMOS technology, which works at 1.8V power supply. This design was then used to design an 8 bit SEU tolerant Serial in Serial out (SISO) Shift Register. Though SEU tolerant D flip flops have been designed in the past [4], we need control signals also implemented in the SEU tolerant circuit like Preset and Clear signals for implementation in synchronous circuits like a Shift Register. A few memory latches such as the Barry-Dooley, DICE, Double Dice, Quarto-10T [5] etc were exploited to explore the feasibility of Preset-Clear master-slave D flip flop. The logic was controlled in this circuit using the variation in device geometries. The change in width/length reflects the change in current passing through the feedback node and hence masking the current logic state respective to either preset or clear inputs. In this thesis, along with other conventional designs, a new circuit architecture was proposed and implemented to achieve the purpose of control signal included D flip flop design. It was found that the current through output node ranges from 30 to 50 uA while operating in 0 to 1.8 V dynamic range, but on particle strike the current burst on critical node reaches up to 1-5 mA. Only Barry-Dooley and DICE cells were found suitable for modified circuit operation. For this simulation environment, the particle strike was considered to have a peak critical charge up to 100pC for a duration of 50 ns. For this study, Cadence design tool was used for circuit simulation and the results were verified with post layout simulations. In addition, process variation simulations were also done for all the circuits