For medium speed and medium resolution application Successive Approximation Register (SAR) Analog to Digital Converters (ADC) are preferred because of tradeof between sampling frequency and number of bits. In SAR ADC a feedback Digital to analog converter (DAC) is required. The output this DAC is approximated to analog input signal through an iterative process. The conventional DAC are made of resistor. R–2Rladder and weighted resistor are types of resistive DAC. Use of resistor in integrated circuit (IC) requires larger area. These resistors also consume more static power. Generally DAC used in SAR ADC is made of capacitor rather than resistor for IC implementation. The capacitive DAC consumes power only for duration of their charging. There are many example of capacitive DAC such as C-2C DAC, charge scaling DAC or much other architecture. Some of capacitive DAC also allow to sample on it and it don’t require extra sample and hold circuit. Further different switching schemes are used for example conventional switching and monotonic switching. The comparator used in SAR ADC for high resolution generally consumes high power. Also to make a rail to rail comparator is very difficult. To avoid rail to rail operation differential DAC architecture used in this thesis work and for low voltage difference comparison an autozeroing technique has used. The differential DAC architecture also has many advantages as compareto conventional DAC architecture. Differential architecture doublesthe input voltage range. This architecture has spurious cancellation of even odder harmonics.Common mode sampling is used to maximize to input voltage range. A bootstrapped sampling switch is used here for constant on resistance which is very useful for higher order harmonics. In this thesis, SAR ADC has designed in SCL PDK with 180nm CMOS technology. It works on 1.8V power supply. It has 12 bit resolution and implemented with differential DAC architecture so size of 1LSB is computed to be 0.88mV. Without effecting system parameter maximum sampling frequency is found to be 1.1-MS/s (mega samples per second). SNDR (signal to noise and distortion ratio) of this ADC is calculated to be 73.54dB. Using this SNDR, effective no of bits is calculated to be 11.92 bits. FOM (Figure of merit) is calculated to be 44fJ/conversion step. The maximum differential non linearity (DNL) and integral non linearity (INL) measured to 0.8 least significant bits (LSB) and 3 LSB respectively.