Optimized Performance and Load Balanced Dynamic Task Scheduling Scheme for Heterogeneous Multi-core Architecture (Record no. 16063)

MARC details
000 -LEADER
fixed length control field 00646nam a2200169Ia 4500
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 240319s9999 xx 000 0 und d
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.395
Item number B575O
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Bharadwaj, Mukesh
9 (RLIN) 41682
245 ## - TITLE STATEMENT
Title Optimized Performance and Load Balanced Dynamic Task Scheduling Scheme for Heterogeneous Multi-core Architecture
Statement of responsibility, etc. by Mukesh Bharadwaj
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Place of publication, distribution, etc. IIT Jodhpur
Name of publisher, distributor, etc. Department of Electrical Engineering
Date of publication, distribution, etc. 2021
300 ## - PHYSICAL DESCRIPTION
Extent v;29p.
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Heterogeneous Multi-core Architecture
9 (RLIN) 41683
Topical term or geographic name entry element Department of Electrical Engineering
9 (RLIN) 41684
Topical term or geographic name entry element MTech Theses
9 (RLIN) 41685
700 ## - ADDED ENTRY--PERSONAL NAME
Personal name Fulwani, Deepak
9 (RLIN) 41686
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type Thesis
Source of classification or shelving scheme Dewey Decimal Classification
Holdings
Withdrawn status Lost status Damaged status Not for loan Home library Current library Shelving location Date acquired Total Checkouts Full call number Barcode Date last seen Price effective from Koha item type
        S. R. Ranganathan Learning Hub S. R. Ranganathan Learning Hub   19/03/2024   621.395 B575O TM00233 19/03/2024 19/03/2024 Thesis